1. Field of the Invention
An object of the present invention is a method for the testing of electronic components. It can be used more particularly in the field of tests on batches of electronic components when they come off the production line, especially tests made on memory type electronic components and, in particular, flash memory type components. In the prior art, there are known methods that are repeated identically on components of one and the same type, these components coming from one and the same manufactured batch, or from one or more production lines. The value of the invention lies in the fact that it proposes a method of testing that gradually reduces the time taken to perform one and the same test on one and the same type of component.
2. Description of the Prior Art
In the prior art, there is a known machine for testing electronic components such as memory components of an integrated circuit. In general, at an output of a production line, components are arranged on wafers. A wafer may comprise up to a hundred memory components to be tested. Each of the memory components is tested integrally, and the test is performed individually and independently of the other tests to be made on other components of the wafer.
An electronic component comprises chiefly cells and inputs and outputs. These inputs and outputs are used for communication with inputs and outputs of cells. For example, a memory component may be constituted by 256 K memory cells such that each of the memory cells has an input and an output. Furthermore, this memory component may comprise, in one example, 32 inputs and 32 outputs. In general, a memory cell of an electronic component such as this is a transistor. In one example, this transistor may have eight different output states. In this example, for memory components to be tested, a memory cell may be positioned at eight distinct voltage levels. These levels can range from 1.5 to 2.5 volts, depending on the size of the memory components. A voltage level of the memory cell is then encoded in three bits.
In the prior art, there are therefore known testing machines capable of successively performing tests on each memory cell of a memory to ascertain that the memory component is valid. The nature and the modalities of the performance of the tests are generally defined beforehand on a theoretical basis. In particular, in theoretical terms, a historical pattern of tests to be sent in each of the cells to be tested is provided and, in theoretical terms, as a function of these tests, patterns of states are defined. Given the nature and the historical pattern of the initial signal sent, the memory cell must theoretically pass through these patterns of states.
Since the historical patterns of the theoretical tests are set up when starting, during the designing of a component, the testing times determined for the testing of this component allow for considerable safety margins as regards the success of the tests. Furthermore, the historical test patterns and their period of implementation do not take account of the improvements achieved in production. Indeed, a modification of one of the historical test patterns or of its duration may have consequences that are hard to assess theoretically. Hence, the historical patterns of the initial historical tests are not modified or, if they are, it is very rare that it is done. The durations of the tests are therefore given values substantially in excess of what they could be. Hence, in the prior art, the performance of such tests on electronic components is a very lengthy process.
In the prior art, there is a known test method to slightly reduce the total testing duration of an electronic component. In this method, several cells of the component are tested simultaneously. Indeed, since a component can have up to 32 inputs it is possible, in this case, to test up to 32 cells simultaneously. Since each test consists in sending a non-monotonic electric signal for a certain duration, signal-coupling problems may appear. Indeed, tests are theoretically defined such that these tests can be sent simultaneously. However, if it is sought to modify some of these tests, there is the risk of emergence of some of these coupling phenomena. Indeed, since the combinations of the different signals sent on the 32 inputs of the component to 32 cells to be tested of this component are excessively complex, they cannot be easily optimized. Hence, the test methods set up in the prior art are kept unchanged, and no system of continuous optimization is set up.
It is an object of the invention to overcome the problems referred to by proposing a test method to gradually optimize the duration of a test performed on an electronic component. The solution of the invention consists of a method to test an electronic component such that, in a first stage, a signal is sent to a cell to be tested of the component. This first signal sent is non-monotonic. Generally, it has a complex shape and is defined by a historical pattern that is a sequence of variations of values in a certain duration.
The signal may be sent, for example, from an analog-digital converter expressing a table of values corresponding to the values of the historical pattern to be processed. The analog-digital converter is then controlled by a clock that defines a speed of transmission of the electrical signal and, therefore, the duration of this signal. This signal is sent to a cell in particular of the component to be tested.
After a certain period of time, the receiver cell sends a response. This response is measured. It is generally an electric signal type of response comprising a pattern of electrical states through which the cell passes under the effect of the received signal. Since, in the particular example referred to, the cell can be placed in eight different states, a pattern of states of the cell can be represented, for example, by a stepped curve with eight levels. Then, an assessment is made to see if this pattern of states obtained is in conformity with an expected pattern of states. In other words, the pattern of states is compared with acceptance criteria that are either lower or higher for elementary steps of the pattern of states.
The method according to the invention proposes that the test should be carried out again by compressing the duration of the historical pattern of the initial signal. Thus the same signal is sent. This signal has, on the whole, the same characteristics as the first signal sent, except that it is done on a smaller duration. As a result, the pattern of states through which the cell passes is obtained more quickly, and this pattern of states itself has a shorter duration. Then, if the pattern of states obtained conforms or does not conform to an equally compressed pattern of states that is expected, the component is accepted or rejected.
The expected pattern of states may be obtained by compressing the initial expected pattern of states in the same way as the initial sent signal was compressed to give the signal with the compressed historical pattern. To reduce the duration of the tests gradually as and when the components are tested, it may be planned for example to take account of this new historical pattern of sent signals as being the signal to be sent to a new component to be tested. In this case, a new component is tested immediately with a compressed testing time.
The invention therefore relates to a method for the testing of an electronic component wherein:
a first signal is sent, with first duration, with a first non-monotonic historical pattern to a first cell of the component,
a measurement is made of a result represented by a first pattern of electric states of the first cell,
the component is accepted if the first pattern of states conforms to an expected pattern,
wherein
the duration of the historical pattern of the first signal is compressed,
a compressed pattern of corresponding states is measured, and
the component is accepted if the compressed pattern of states conforms to an expected compressed pattern.